- BSEE, 1994, Electrical Engineering, Stanford University
- MSEE, 1997, Electrical Engineering, Stanford University
- Ph.D., 2001, Electrical Engineering, Stanford University
- Electrical Engineering
- Computer Engineering and Architecture
- Circuits and VLSI
Primary Teaching Area
Gu-Yeon Wei's research group focuses on various aspects of high-speed, low-power digital and mixed-signal VLSI circuits. Significant advances in modern CMOS technology have enabled highly complex machines capable of executing extremely high levels of computation with performance doubling every few years. However, this performance comes at the cost of higher power dissipation. At the other end of the spectrum, portable electronic devices demand low-power, energy-efficient operation. Wei's research group investigates the interactions between VLSI circuits, computer architecture, and software layers to enhance energy efficiency in future computing systems.
Current research projects span a variety of topics such as integrated voltage regulators and associated computer architecture techniques to maximize its utility; flexible voltage stacking to address power delivery challenges in complex digital systems; power electronics to drive piezoelectric actuators for RoboBees, low-power computing architectures and circuits to serve as the 'brain' for RoboBees; collaborative computer architecture and circuit solutions to address process, voltage, and temperature (PVT) variations; runtime compilers to automatically parallelize inherently sequential code; and others. Prior research efforts focused on high-speed wireline transceivers and related building blocks.
Wei received his B.S.E.E., M.S., and Ph.D. in Electrical Engineering from Stanford University in 1994, 1997, and 2001, respectively. In August 2000, he joined Accelerant Networks (now a part of Synopsys) in Beaverton, Oregon as a Senior Design Engineer, where he worked on a 5-Gbps backplane transceiver with adaptive equalization. As the internet bubble was showing signs of bursting, he joined Harvard University in January 2002.
Besides his research activities, he currently teaches students how to design chips in the VLSI Design course (CS148/CS248) and think about important circuits and systems issues through a graduate-level reading course that covers a wide range of topics related to Mixed-Signal IC Design (ES271r). As of July 1, 2011, Wei also serves as the Associate Dean for Academic Programs at SEAS. Through this position, he hopes to enhance design and hands-on experiential learning throughout the engineering curriculum, and to make Harvard SEAS a vibrant community for future engineers and scientists.
Positions & Employment
Harvard School of Engineering and Applied Sciences
July 2011-Present: Associate Dean for Academic Programs
January 2002-Present: Gordon McKay Professor of Electrical Engineering and Computer Science
August 2000-January 2002: Senior Design Engineer
Low power control IC for efficient high-voltage piezoelectric driving in a flying robotic insect. M. Karpelson, R.J. Wood, and G.-Y. Wei. IEEE Symposium on VLSI Circuits, June 2011.
Energetics of flapping-wing robotic insects: towards autonomous hovering flight. M. Karpelson, J.P. Whitney, G.-Y. Wei, and R.J. Wood. IEEE/RSJ Int. Conference on Intelligent Robots and Systems, 2010.
A fully-integrated 3-level DC/DC converter for nanosecond-scale DVS with fast shunt regulation. Wonyoung Kim, David Brooks, and Gu-Yeon Wei. IEEE International Solid-State Circuits Conference (ISSCC-11), Feb. 2011.
Achieving uniform performance and maximizing throughput in the presence of heterogeneity. Krishna Rangan, Michael Powell, Gu-Yeon Wei, and David Brooks. 17th Annual International Symposium on High-Performance Computer Architecture (HPCA-17), Feb. 2011.
Predicting voltage droops using recurring program and microarchitectural activity. Vijay J. Reddi, Meeta Gupta, Glenn Holloway, Michael D. Smith, Gu-Yeon Wei and David Brooks. IEEE MICRO Top Picks, Jan/Feb 2010.
Voltage Smoothing: Characterizing and mitigating voltage noise in a production processor using software-guided thread scheduling. Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D. Smith, Gu-Yeon Wei, David Brooks. 43rd Annual International Symposium on Microarchitecture (Micro-43), Dec. 2010.
A 8x5Gbps parallel receiver with collaborative timing recovery and clock spacing error correction. Ankur Agrawal, Andrew Liu, Pavan K. Hanumolu and Gu-Yeon Wei. IEEE Journal of Solid-State Circuits (JSSC), Nov 2009.