Vijay Janapa Reddi

Vijay Janapa Reddi

  • Associate Professor of Electrical Engineering


Vijay Janapa Reddi is interested in building intelligent mobile and edge computing systems, specifically in the context of smartphones, IoT devices, and robotics.

He specializes in computer architecture and runtime systems. His unique approach is to break through the traditional abstraction layers that are at the intersection of hardware and software to co-design the system from programming languages down to the bits and gates for a practical (i.e., performance and energy-efficient) domain specific solution. 

His areas of success include dynamic/just-in-time binary instrumentation systems to introspect a program transparently and efficiently, simulation and modeling solutions to design robust and resilient microprocessors, architecting the system for energy-efficient mobile computing, and establishing the role of computing in autonomous machines.

Professor Janapa Reddi received the B.S. degree in Electrical and Computer Engineering in 2003, the M.S. degree in Computer Engineering from the University of Colorado at Boulder, the Ph.D. degree in Computer Science from Harvard University in 2010.

Contact Information

Office:Maxwell Dworkin 147
Assistant:Molly A. Marshall
Assistant Office:Pierce 120
Assistant Phone:(617) 496-2942
Research Mgr: Kathleen Marie Kelley

Primary Teaching Area

Positions & Employment

University of Texas at Austin, Associate Professor, Aug 2017 – Present

University of Texas at Austin, Assistant Professor, Aug 2011 – Jul 2017

Google, Visiting Research Faculty, Mar 2017 – Present

Intel, Consultant, Jun 2015 – Dec 2016

Advanced Micro Devices (AMD), Consultant, Feb 2015 – Dec 2016

Intel, Consultant, Jun 2014 – Aug 2014

Advanced Micro Devices (AMD), Senior Design Engineer, Jul 2010 – Jul 2011

Microsoft Research, Research Intern, Mar 2009 – Jun 2009

VMware, Research Intern, Jan 2007 – Mar 2009

Intel, Research Intern, Apr 2003 – Dec 2006

Other Experience & Professional Membership

Member: Institute of Electrical and Electronics Engineers (IEEE)

Member: Association for Computing Machinery (ACM)


  • Associate Editor, SIGARCH Blog
  • General Chair, Intl. Symp. on Code Generation and Optimization (CGO 2017)
  • ACM SRC Chair, Intl. Symp. Parallel Architectures and Compilation Techniques (PACT 2017)
  • Finance Chair, Intl. Symp. on Code Generation and Optimization (CGO 2015)
  • Program Committee:
    • Arch. Support for Programming Languages and Operating Systems (ASPLOS 2018)
    • IEEE Micro Top Picks (2016, 2018)
    • Intl. Symp. on Computer Architecture (ISCA 2014)
    • High Performance Computer Architecture (HPCA 2012, 2014, 2015, 2017erc)
    • Microarchitecture (MICRO 2013, 2014, 2018)
    • Principles and Practice of Parallel Computing (PPoPP 2013, 2015)
    • Code Generation and Optimization (CGO 2013, 2014)
    • Parallel Architectures and Compilation Techniques (PACT 2013)
    • Workload Characterization (IISWC 2012, 2013, 2016, 2018)
    • Parallel & Distributed Processing (IPDPS 2012)
    • Performance Analysis of Systems and Software (ISPASS 2012)
  • Program Chair, Intl. Symp. on Code Generation and Optimization (CGO 2014)
  • Guest Editor,
    • IEEE Micro Special Issue on Reliability-Aware Microarchitecture Design (2013),
    • IEEE Micro Special Issue on Internet of Things (2016)
  • Local Arrangements Chair,
    • Intl. Symp. on Performance Analysis of Systems and Software (ISPASS 2013)
    • Workshop on Silicon Errors in Logic - System Effects (SELSE 2015, 2016)
  • Publications Chair, Intl. Symp. on Workload Characterization (IISWC 2013)
  • Organizer
    • Workshop on Cognitive Edge Computing (CogEdge 2016-2017)
    • Tutorial on Tools for Mobile Computer Architecture (MobiTools 2016)
    • Tutorial on Simulation and Analysis Engine (ISCA 2016, ASPLOS 2016, HPCA 2016, ICS 2016, IISWC 2015, ISPASS 2015)
    • Workshop on Resilient Architectures (WRA 2013–2010)
  • Steering Committee, Intl. Symp. on Code Generation and Optimization (CGO)


• SIGARCH CS TCCA Outstanding Dissertation Award (Advisee: Yuhao Zhu), SIGARCH, 2018.

• Top Picks in Computer Architecture, IEEE Micro, 2017.

• Google Faculty Research Award, Google, 2012, 2013, 2015, 2017.

• IEEE TCCA Young Computer Architect Award, IEEE Computer Society, 2016.

• Top Picks in Computer Architecture (Honorable Mention), IEEE Micro, 2016.

• Gilbreth Lectureship Honor, National Academy of Engineering (NAE), 2016.

• Most Influential PLDI Paper Award, ACM SIGPLAN, 2015.

• Best of Computer Architecture Letters (CAL) Award, Editorial Board of IEEE CAL, 2014

• Indo-American Frontiers of Engineering, National Academy of Engineering (NAE), 2014.

• Intel Early Career Honor Award, Intel, 2013.

• Top Picks in Computer Architecture, IEEE Micro, 2011.

• Top Picks in Computer Architecture, IEEE Micro, 2010.

• Best Paper Award, Intl. Symp. on High Performance Computer Architecture (HPCA), 2009.

• John A. and Elizabeth S. Armstrong Fellowship, Harvard University, 2008.

• Best Student Presentation, Intl. Symp. on Code Generation and Optimization (CGO), 2007.

• Top Picks in Computer Architecture, IEEE Micro, 2006.

• Best Paper Award, International Symposium on Microarchitecture (MICRO), 2005.

• Faculty Recognition for Technical Excellence, Santa Clara University, 2003.

• Outstanding Undergraduate (Honorable), Computing Research Association (CRA), 2003.

Patents Awarded

  • P1. R. Cohn, T. Moseley, and V. Janapa Reddi. “System and method to instrument references to shared memory.” U.S. Patent Application 11/143,130, filed June 1, 2005.
  • P2. N. Kim, J. O’Connor, M. Schulte, and V. Janapa Reddi. “Method and apparatus for power reduction during lane divergence.” U.S. Patent Application 13/605,460, filed September 6, 2012.
  • P3. V. Janapa Reddi, M. Gupta, G. Holloway, G. Wei, M. D. Smith, and D. Brooks. “Adaptive event-guided system and method for avoiding voltage emergencies.” U.S. Patent 8,949,666, issued February 3, 2015.